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ADRF6614ACPZ-R7 데이터시트(PDF) 9 Page - Analog Devices

부품명 ADRF6614ACPZ-R7
상세설명  700 MHz to 3000 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO
PDF  61 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADRF6614ACPZ-R7 데이터시트(HTML) 9 Page - Analog Devices

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Data Sheet
ADRF6614
Rev. 0 | Page 9 of 61
DIGITAL LOGIC SPECIFICATIONS
Table 7.
Symbol
Description
Min
Typ
Max
Unit
tCLK
Serial clock period
38
ns
tDS
Setup time between data and rising edge of SCLK
8
ns
tDH
Hold time between data and rising edge of SCLK
8
ns
tS
Setup time between falling edge of CS and SCLK
10
ns
tH
Hold time between rising edge of CS and SCLK
10
ns
tHIGH
Minimum period for SCLK to be in a logic high state
10
ns
tLOW
Minimum period for SCLK to be in a logic low state
10
ns
tACCESS
Maximum delay between falling edge of SCLK and output data Valid for a read operation
231
ns
tZ
Maximum delay between CS deactivation and SDIO bus return to high impedance
5
ns
tS
tDS
tDH
tHIGH
tLOW
tCLK
tH
DON'T CARE
DON'T CARE
A5
A4
A3
A2
A1
A0
D15
D14
D13
D3
D2
D1
D0
DON'T CARE
DON'T CARE
SCLK
SDIO
R/W
tZ
tACCESS
A6
CS
Figure 2. Setup and Hold Timing Measurements



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