NAND01GR3B datasheet(33/64 Pages) STMICROELECTRONICS

33 / 64 page

NAND01G-B, NAND02G-B

Device operations

33/64

6.8

Read Status Register

The device contains a Status Register which provides information on the current or previous

Program or Erase operation. The various bits in the Status Register convey information and

errors on the operation.

The Status Register is read by issuing the Read Status Register command. The Status

Enable or Read Enable, whichever occurs last. When several memories are connected in a

system, the use of Chip Enable and Read Enable signals allows the system to poll each

device separately, even when the Ready/Busy pins are common-wired. It is not necessary to

toggle the Chip Enable or Read Enable signals to update the contents of the Status

After the Read Status Register command has been issued, the device remains in Read

Status Register mode until another command is issued. Therefore if a Read Status Register

command is issued during a Random Read cycle a new Read command must be issued to

continue with a Page Read operation.

The Status Register bits are summarized in Table 13: Status Register Bits,. Refer to

Table 13 in conjunction with the following text descriptions.

6.8.1

Write Protection Bit (SR7)

The Write Protection bit can be used to identify if the device is protected or not. If the Write

Protection bit is set to ‘1’ the device is not protected and program or erase operations are

allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase

operations are not allowed.

6.8.2

P/E/R Controller and Cache Ready/Busy Bit (SR6)

Status Register bit SR6 has two different functions depending on the current operation.

During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which

indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0',

the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to

accept new data.

During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the

P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R

Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive

(device is ready).

6.8.3

P/E/R Controller Bit (SR5)

The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or

inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is

busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready).

NAND01GR3B 데이터시트(PDF) 33 Page - STMicroelectronics