M69KB096AA

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Deep Power-Down Mode. Deep

power-down

(DPD) mode is used by the system memory con-

troller to de-activate the PSRAM device when its

storage capabilities are not needed. All refresh-re-

lated operations are then disabled. When the

Deep Power-Down mode is enabled, the data

stored in the device become corrupted. When re-

fresh operations have been re-enabled, the device

(time to perform an initialization sequence). During

this delay, the current consumption will be higher

than the specified standby levels, but considerably

lower than the active current.

Figure 4. Synchronous Burst Read Mode

Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

A0-A21

WAIT

DQ0-DQ15

Latency Code 2 (3 clocks)

K

Burst Read Identified

(W = High)

Address

Valid

AI06774b

ADV

E

G

W

Hi Z

Hi Z

LB/UB

DQ0

DQ1

DQ2

DQ3