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M69KB096AA

Table 15. Asynchronous Read AC Characteristics

Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).

2. The timing is related to Asynchronous Page mode only.

3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a

4. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a

Symbol

Alt.

Parameter

M69KB096AA

Unit

70ns

85ns

Min

Max

Min

Max

Address Valid to Output Valid

70

85

ns

L Low to Output Valid

70

85

ns

Page Access Time

20

25

ns

L High to Address Transition

5

5

Address Valid to L High

10

10

Upper/Lower Byte Enable Low to Output

Valid

70

85

ns

(4)

Upper/Lower Byte Enable High to Output Hi-

Z

88

ns

(3)

Upper/Lower Byte Enable Low to Output

Transition

10

10

ns

Chip Enable High between Subsequent

Mixed-Mode Read Operations

55

ns

(2)

Maximum Chip Enable Pulse Width

8

8

µs

Chip Enable Low to WAIT Valid

1

7.5

1

7.5

ns

Chip Enable high to WAIT High-Z

8

8

ns

Chip Enable Low to Output Valid (Chip

Select Access Time)

70

85

ns

Chip Enable Low to L High

10

10

ns

(4)

Chip Enable High to Output Hi-Z

8

8

ns

(3)

Chip Enable Low to Output Transition

10

10

ns

Output Enable Low to Output Valid

20

20

ns

Output Enable High to Output Transition

5

5

ns

Data Hold from Address Change

5

5

ns

(4)

Output Enable High to Output Hi-Z

8

8

ns

(3)

Output Enable Low to Output Transition

5

5

ns

Page Cycle Time

20

25

Read Cycle Time

70

85

ns

L Pulse Width Low

10

10

ns

L Pulse Width High

10

10

ns