M69KB096AA

12/48

Figure 7. Collision between Refresh and Write Operation

Note: Additional Wait states inserted to allow Refresh completion.

Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

A0-A21

WAIT

DQ0-DQ15

K

Additional WAIT states inserted

to allow Refresh completion

Address

Valid

AI06777

E

G

W

Hi Z

Hi Z

LB/UB

DQ0

DQ1

DQ2

DQ3

L