ATXP032 datasheet(66/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

impedance typically allows higher speed operation and/or higher capacitive load, while higher impedance reduces

overall power consumption and switching noise.

12.5

Read Status Registers (65h)

All Status/Control registers may be read out by using the generic Read Status Registers command. This command

allows for a readout of all Status/Control registers in one operation.The Status/Control registers can be read at any

time, including during an internally self-timed program or erase operation.

The Status/Control registers can be sequentially read in a similar fashion to the read array operation up to the

maximum clock frequency specified by f

CLK. To read the Status/Control registers, the CS pin must first be asserted

and the command of 65h must be clocked into the device. After the command has been clocked in, one address

byte must be clocked in to specify which register to read. Following the address byte, one or more additional

dummy bytes need to be clocked into the device. For the SPI mode, one dummy byte (8 cycles) is used. For octal

SDR mode, 4 dummy cycles are used (3.5 dummy cycles for octal DDR).

Table 12-10. I/O Pin Strength Control Register

Bit

Acronym

Name

Type (1)

Default

Description

Reserved for future use

2:0

IOD2

I/O Drive Select 2

R/W

See

Table 12-11

IOD1

I/O Drive Select 1

R/W

IOD0

I/O Drive Select 0

R/W

R/W = Readable and writable

R = Readable only

Table 12-11. I/O Driver Strength Types — IOD[2:0]

IOD2

IOD1

IOD0

Driver Type

Value

Nominal

Impedance

Approximate driving capability

compared to Type-0

Remarks

0x00

50 Ω

Default

0x01

33 Ω

x1.5

Supports highest load / speed

0x02

66 Ω

x0.75

Supports lower energy

consumption

0x03

100 Ω

x0.5

Supports lowest energy

consumption

0x04

40 Ω

x1.2

Supports higher load / speed

N/A

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