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ATXP032

DS-ATXP032–114I–4-2020

13.10 Hardware Reset

The hardware reset pin (RESET) can be used to wake up the device from Ultra-Deep Power-Down (UDPD) mode.

This sequence can also be used to reset the device to a state similar to the power-on state without cycling power.

The differences between the power-on state and the reset state are described below.

The reset sequence in this case does not use any other pins. A low state on the reset pin (RESET) terminates the

operation in progress and resets the internal state machine to an idle state. The device remains in the reset

condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is

brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions

on the RESET pin during power-on sequences.

After a hardware reset initiated by the RESET pin while the device is in UDPD mode, the SRAM buffer resets to an

undefined value. All volatile Status/Control registers, including the sector protection bits, are reset to their default

values, except in the following case: If the AUDPD bit in Status Register Byte 2 was set prior to the last Program or

Erase command, so the device entered the Ultra-Deep Power-Down mode after a Program or Erase command

finished, and RESET is used to wake up the device from Ultra-Deep Power-Down mode, then the EPE bit will not

be reset. In this case the EPE still shows the correct status after the latest Program or Erase command. All non-

volatile Status/Control registers keep the value they had prior to reset.

After a Hardware Reset initiated by the RESET pin while the device is in any other mode than Ultra-Deep Power-

Down mode, the SRAM buffer will keep the values it had prior to Reset, with the following exception: If the Reset

sequence is initiated during an update of the SRAM buffer, the contents of the SRAM buffer may be corrupted. All

volatile Status/Control registers are reset to their default values, except the sector protection bits. The sector

protection bits remain unchanged in this case. All non-volatile Status/Control registers keep the value they had

prior to reset, with the following exception: If the reset sequence is initiated during a write to a non-volatile

Status/Control register, the value of that register may be corrupted.

The device always reverts back to standard SPI mode after RESET.

Figures 13-15 and 13-16 below illustrates the timing for the hardware RESET sequence. See AC Characteristics,

All Other Parameters for details on reset timing.

Figure 13-15. Hardware Reset Sequence

Note: The CS signal should be in the high state before the RESET signal is deasserted.

SCK

RESET

SO (Output)

High-impedance

SI (Input)

tRST

tREC

tCSLS

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