DS20006554A datasheet(31/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

6.1.3

Multiregister Fields

Multiregister fields

—such as AFBDIV[41:0] in registers AFBDIV1 through AFBDIV6—must be handled carefully to

ensure that the bytes of the field remain consistent during writes. A write access to a multiregister field is

accomplished by writing all the registers of the field in order from smallest address to largest. Writes to registers other

than the last register in the field (i.e. the register with the largest address) are stored in a transfer register. When the

last register of the field is written, the entire multiregister field is updated simultaneously from the transfer register. If

the last register of the field is not written, the field is not updated.

Read accesses from multiregister fields are the same as normal registers since the multiregister fields are not

modified by the device.

An exception for AFBDIV happens when AFBDL.RDCUR=1. In this case reads come directly from the internal logic

and don’t affect the transfer register. Writes behave the same as above.

The multiregister fields are:

Field

Registers

Type

AFBDIV[41:0]

AFBDIV1 to AFBDIV6

Read/Write

FDIV[39:0]

F1DIV1 to F1DIV5

Read/Write

6.1.4

Bank-Switched Registers (ZL30261 and ZL30263 Only)

The EESEL register is a bank-select control field that maps the device registers into the memory map at address 0x1

and above when the EESEL bit is 0 and maps the EEPROM memory into the memory map at address 0x1 and above

when the EESEL bit is 1. The EESEL register itself is always in the memory map at address 0x0.

6.2

Table 4 - Register Map

ADDR

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Global Configuration Registers

00h

EESEL

—

MCR1

SRST

HRST

STOP

—

ROSCD

AINCDIS

ODMISO

—

MCR2

XAMCK

IC3MCK

IC2MCK

IC1MCK

—

DBL

XAB[1:0]

PLLEN

—

APLLEN

ICEN

—

IC3EN

IC2EN

IC1EN

OCEN1

OC8EN

OC7EN

OC6EN

OC5EN

OC4EN

OC3EN

OC2EN

OC1EN

OCEN2

—

OC10EN

OC9EN

OCMUX1

—

OCMUXC[1:0]

OCMUXB[1:0]

OCMUXA[1:0]

OCMUX2

—

OCMUXF[1:0]

OCMUXE[1:0]

OCMUXD[1:0]

STOPCR1

OC8

OC7

OC6

OC5

OC4

OC3

OC2

OC1

STOPCR2

—

OC10

OC9

GPIOCR1

GPIO1C[3:0]

GPIO0C[3:0]

GPIOCR2

GPIO3C[3:0]

GPIO2C[3:0]

GPIO0SS

REG[4:0]

BIT[2:0]

GPIO1SS

REG[4:0]

BIT[2:0]

GPIO2SS

REG[4:0]

BIT[2:0]

GPIO3SS

REG[4:0]

BIT[2:0]

I2CA

—

I2CA[6:0]

Status Registers

ID1

IDU[7:0]

ID2

IDL[3:0]

REV[3:0]

CFGSR

CFGD

—

IF[1:0]

TEST

AC[2:0]

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