DS20006554A datasheet(14/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

5.5.4

APLL Output Frequency

Figure 5 - APLL Block Diagram

The APLL is enabled when PLLEN.APLLEN=1. The APLL has a fractional-N architecture and therefore can produce

output frequencies that are either integer or non-integer multiples of the input clock frequency. Figure 5 shows a

block diagram of the APLL, which is built around an ultra-low-jitter multi-GHz VCO. Register fields AFBDIV, AFBREM,

AFBDEN and AFBBP configure the frequency multiplication ratio of the APLL. The ACR2.INTDIV field specifies how

the VCO frequency is divided down by the

APLL’s integer divider (which can also do some half divides). Dividing by

6 is the typical setting to produce 622.08MHz for SDH/SONET or 625MHz for Ethernet applications. The configuration

registers for the APLL’s fractional divider are described in section 5.5.5.

Internally, the exact APLL feedback divider value is expressed in the form AFBDIV + AFBREM / AFBDEN * 2-(33-AFBBP).

This feedback divider value must be chosen such that APLL_input_frequency * feedback_divider_value is in the

operating range of the VCO (as specified in Table 14). The AFBDIV term is a fixed-point number with 9 integer bits

and a configurable number of fractional bits (up to 33, as specified by AFBBP). Typically AFBBP is set to 9 to specify

that AFBDIV has 33

– 9 = 24 fractional bits. Using more than 24 fractional bits does not yield a detectable benefit.

Using less than 12 fractional bits is not recommended.

The following equations show how to calculate the feedback divider values for the situation where the APLL should

multiply the APLL input frequency by integer M and also fractionally scale by the ratio of integers N / D. In other

words, VCO_frequency = input_frequency * M * N / D. An example of this is multiplying 77.76MHz by M=48 and

scaling by N / D = 255 / 237 for forward error correction applications.

afbdiv = trunc(M * N / D * 224)

(1)

lsb_fraction = M * N / D * 224

– afbdiv

(2)

AFBDEN = D

(3)

AFBREM = round(lsb_fraction * AFBDEN)

(4)

AFBBP = 33

– 24 = 9

(5)

AFBDIV[41:0] = afbdiv * 2AFBBP

(6)

The trunc() function returns only the integer portion of the number. The round() function rounds the number to the

nearest integer. In Equation (1),

the temporary variable ‘afbdiv’ is set to the full-precision feedback divider value, M

* N / D, truncated after the 24th fractional bit. In Equation (2) the temporary variable 'lsb_fraction' is the fraction that

was truncated in Equation (1) and therefore is not represented in the afbdiv value. In Equation (3), AFBDEN is set to

the denominator of the original M * N / D ratio. In Equation (4), AFBREM is calculated as the integer numerator of a

fraction (with denominator AFBDEN) that equals the 'lsb_fraction' temporary variable. In Equation (5) AFBBP is set

to 33

– 24 = 9 to correspond with AFBDIV having 24 fractional bits. Finally, in equation (6) the afbdiv bits are shifted

into the proper position for the AFBDIV registers.

APLL

Phase/

Freq

Detector

Loop

Filter

VCO

~3.7- 4.2

GHz

Feedback

Divider

(fractional)

AFBDIV[74:0], AFBREM,

AFBDEN, AFBBP

Input Frequency Range:

9.72MHz to 156.25MHz

Clock from APLL

Input Mux

Integer

Divider

(whole ÷ 4-15,

half ÷ 4.5-7.5)

Clock to

Output

Muxes

ACR2.INTDIV[3:0]

Fractional

Divider

Clock to

Output

Muxes

FDIV, FREM, FDEN, FBP

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