전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

DS20006554A 데이터시트(PDF) 84 Page - Microchip Technology

부품명 DS20006554A
상세설명  1-APLL, 6- or 10-Output Any-to-Any Clock Multiplier and Frequency Synthesizer
PDF  94 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DS20006554A 데이터시트(HTML) 84 Page - Microchip Technology

Back Button DS20006554A Datasheet HTML 80Page - Microchip Technology DS20006554A Datasheet HTML 81Page - Microchip Technology DS20006554A Datasheet HTML 82Page - Microchip Technology DS20006554A Datasheet HTML 83Page - Microchip Technology DS20006554A Datasheet HTML 84Page - Microchip Technology DS20006554A Datasheet HTML 85Page - Microchip Technology DS20006554A Datasheet HTML 86Page - Microchip Technology DS20006554A Datasheet HTML 87Page - Microchip Technology DS20006554A Datasheet HTML 88Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 84 / 94 page
background image
ZL30260-ZL30263
Data Sheet
84
© 2021 Microchip Technology Inc.
DS20006554A
Table 19 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers
VDDIO = 3.3V±5% or 2.5V±5% or 1.8V±5%
Characteristics (Notes 1 to 3)
Symbol
VDDIO 3.3V or 2.5V
VDDIO 1.8V
Units
Notes
Min.
Typ.
Max.
Min.
Typ.
Max.
SCLK frequency
fBUS
23
15
MHz
SCLK cycle time
tCYC
43.5
66
ns
CSN setup to first SCLK edge
tSUC
10
10
ns
CSN hold time after last SCLK edge
tHDC
10
10
ns
CSN high time
tCSH
25
25
ns
SCLK high time
tCLKH
10
33
ns
SCLK low time
tCLKL
21.75
33
ns
MOSI data setup time
tSUI
2
10
ns
MOSI data hold time
tHDI
2
10
ns
MISO enable time from SCLK edge
tEN
0
0
ns
MISO disable time from CSN high
tDIS
80
80
ns
MISO data valid time
tDV
20.5
32
ns
MISO data hold time from SCLK edge
tHDO
0
0
ns
CSN, MOSI input rise time, fall time
tR, tF
10
10
ns
Note 1:
All timing is specified with 100pF load on all SPI pins.
Note 2:
All parameters in this table are guaranteed by design or characterization.
Note 3:
See timing diagram in Figure 18.
Figure 18 - SPI Slave Interface Timing
CSN
SCLK
tSUC
tCYC
tCLKL
tCLKH
tSUI
tHDI
MOSI
MISO
tEN
tHDO
tDV
tHDC
tDIS
tCSH



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com