38B5 datasheet(11/70 Pages) RENESAS

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MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

I/O Ports

[Direction Registers] PiD

The 38B5 group has 55 programmable I/O pins arranged in eight

individual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O ports

have direction registers which determine the input/output direction of

each individual pin. Each bit in a direction register corresponds to

one pin, and each pin can be set to be input port or output port. When

“0” is written to the bit corresponding to a pin, that pin becomes an

input pin. When “1” is written to that pin, that pin becomes an output

pin. If data is read from a pin set to output, the value of the port

output latch is read, not the value of the pin itself. Pins set to input

(the bit corresponding to that pin must be set to “0”) are floating and

the value of that pin can be read. If a pin set to input is written to, only

the port output latch is written to and the pin remains floating.

[High-Breakdown-Voltage Output Ports]

The 38B5 group microprocessors have 5 ports with high-breakdown-

voltage pins (ports P0–P3 and P80–P83). The high-breakdown-volt-

age ports have P-channel open-drain output with Vcc- 45 V of break-

down voltage. Each pin in ports P0, P1, and P3 has an internal pull-

down resistor connected to VEE. At reset, the P-channel output tran-

sistor of each port latch is turned off, so that it goes to VEE level (“L”)

by the pull-down resistor.

Writing “1” (weak drivability) to bit 7 of the FLDC mode register (ad-

dress 0EF416) shows the rising transition of the output transistors for

reducing transient noise. At reset, bit 7 of the FLDC mode register is

set to “0” (strong drivability).

[Pull-up Control Register] PULL

Ports P5, P61–P65, P7, P84–P87 and P9 have built-in programmable

pull-up resistors. The pull-up resistors are valid only in the case that

the each control bit is set to “1” and the corresponding port direction

registers are set to input mode.

Fig. 8 Structure of Pull-up Control Registers (PULL1 and PULL2)

0: No pull-up

1: Pull-up

Pull-up control register 2

(PULL2 : address 0EF1 16)

P70, P71 pull-up control bit

P72, P73 pull-up control bit

P74, P75 pull-up control bit

P76, P77 pull-up control bit

P84, P85 pull-up control bit

P86, P87 pull-up control bit

P90, P91 pull-up control bit

Not used

(returns “0” when read)

0: No pull-up

1: Pull-up

Pull-up control register 1

(PULL1 : address 0EF0 16)

P50, P51 pull-up control bit

P52, P53 pull-up control bit

P54, P55 pull-up control bit

P56, P57 pull-up control bit

P61 pull-up control bit

P62, P63 pull-up control bit

P64, P65 pull-up control bit

Not used

(returns “0” when read)

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