PC8374L datasheet(39/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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Figure 4. Structure of Standard Conﬁguration Register File

Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non-existing

which returns 04h (indicating no DMA channel). The configuration registers are accessible immediately after reset.

3.2.3

Standard Configuration Register Definitions

In the registers below, any undefined bit is reserved. Unless otherwise noted, the following definitions also hold true:

• All registers are read/write.

• All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify these

bits. Use read-modify-write to prevent the values of reserved bits from being changed during write.

• Write-only registers must not use read-modify-write during updates.

Table 9. Logical Device Number (LDN) Assignments

LDN

Functional Block

00h

Floppy Disk Controller (FDC)

01h

Parallel Port (PP)

02h

Serial Port 2 (SP2) and InfraRed Port

03h

Serial Port 1 (SP1)

04h

System Wake-Up Control (SWC)

05h

Keyboard and Mouse Controller (KBC) - Mouse Interface

06h

Keyboard and Mouse Controller (KBC) - Keyboard Interface

07h

General-Purpose I/O (GPIO) Ports

08h

Health Management

07h

30h

60h

75h

FFh

Logical Device Number Register

SuperI/O Configuration Registers

Logical Device Control Register

Standard Logical Device

Special (Vendor-Defined)

Configuration Registers

Banks

2Fh

F0h

Bank Select

63h

74h

70h

71h

Configuration Registers

(One per Logical Device)

Logical Device

10h

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