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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC8374L 데이터시트(PDF) 79 Page - National Semiconductor (TI) |
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PC8374L 데이터시트(HTML) 79 Page - National Semiconductor (TI) |
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79 / 239 page  3.0 Device Architecture and Configuration (Continued) Revision 1.1 79 www.national.com 3.15 HEALTH MANAGEMENT (HM) CONFIGURATION 3.15.1 General Description 3.15.2 Logical Device 8 (HM) Configuration Table 33 lists the configuration registers that affect the Health Management Module. See Section 3.2.3 on page 39 for a detailed description of these registers. The standard configuration registers are powered by VDD3; however, the specific con- figuration registers are powered by VSB3. 3.15.3 Health Management Configuration Register 1 (HMCFG1) This register is reset to 01h. Power Well: Varies per bit Location: Index F0h Type: Varies per bit Note: The FANOUTx_INV bits are configurable via the HM module runtime registers. Table 33. Health Management (HM) Configuration Registers Index Configuration Register or Action Type Power Well Reset 30h Activate. When bit 0 is cleared, the runtime registers of this logical device are not accessible (see Section 3.3.1 on page 48).1 1. The logical device runtime registers are maintained and all sensor monitoring mechanisms are functional. R/W VDD3 00h 50h Memory Base Descriptor. R/W VDD3 00h 60h HM_LPC Base Address MSB register. R/W VDD3 00h 61h HM_LPC Base Address LSB register. Bits 3-0 (for A3-0) are read-only, ‘0000’. R/W VDD3 00h 70h Interrupt Number. R/W VDD3 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read-only. R/W VDD3 03h 74h Report no DMA assignment. RO VDD3 04h 75h Report no DMA assignment. RO VDD3 04h F0h Health Management Configuration register 1 (HMCFG1). Varies per bit VSB3 05h Bit 76543210 Name LOCKHCF FANOUT2_ OTYPE FANOUT2_ INV FANOUT1_ OTYPE FANOUT1_ INV FANOUT0_ OTYPE FANOUT0_ INV INT_PU_EN Reset 00000001 Power Well VDD3 VBAT 1 1. See Sections 2.1 and 2.2 VBAT 1 VBAT 1 VBAT 1 VBAT 1 VBAT 1 VSB3 Bit Type Description 7 R/W1S LOCKHCF (Lock Health Management Configuration). When set to 1, locks the bits of HMCFG1 register (including LOCKHCF bit itself) by disabling writing to them. Once set, this bit can be cleared by Hardware reset. 0: R/W bits are enabled for write (default) 1: All bits are RO Winbond Electronics Corp. Advanced PC Product Center |
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