MCP79522-ISLASHMS datasheet(41/58 Pages) MICROCHIP

41 / 58 page

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DS20002300D-page 41

MCP7951X/MCP7952X

6.3.2

EEPROM READ SEQUENCE

The device is selected by pulling CS low. The 8-bit

EEREAD instruction is transmitted to the MCP795XX

followed by an 8-bit address. See Figure 6-8 for more

details.

After the correct EEREAD instruction and address are

sent, the data stored in the EEPROM at the selected

address is shifted out on the SO pin. Data stored in the

memory at the next address can be read sequentially

by continuing to provide clock pulses to the client. The

internal Address Pointer automatically increments to

the next higher address after each byte of data is

shifted out. When the highest address is reached, the

address counter rolls over to address 00h allowing the

read cycle to be continued indefinitely. The read

operation is terminated by raising the CS pin

(Figure 6-8).

6.3.3

EEPROM WRITE SEQUENCE

Prior to any attempt to write data to the MCP795XX

EEPROM, the write enable latch must be set by issuing

the EEWREN instruction. This is done by setting CS low

and then clocking out the proper instruction into the

MCP795XX. After all eight bits of the instruction are

transmitted, CS must be driven high to set the write

enable latch. If the write operation is initiated

immediately after the EEWREN instruction without CS

driven high, data will not be written to the array since

the write enable latch was not properly set.

After setting the write enable latch, the user may

proceed by driving CS low, issuing an EEWRITE

instruction, followed by the address and then the data

to be written. Up to 8 bytes of data can be sent to the

device before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page.

Additionally, a page address begins with XXXX x000

and ends with XXXX x111. If the internal address

counter reaches XXXX

x111 and clock signals

continue to be applied to the chip, the address counter

will roll back to the first address of the page and

over-write any data that previously existed in those

locations.

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

of the nth data byte has been clocked in. If CS is driven

high at any other time, the write operation will not be

completed. Refer to Figure 6-9 and Figure 6-10 for

more detailed illustrations on the byte write sequence

and the page write sequence respectively. While the

write is in progress, the STATUS register may be read

to check the status of the WIP, WEL, BP1 and BP0 bits.

Attempting to read a memory array location will not be

possible during a write cycle. Polling the WIP bit in the

STATUS register is recommended in order to

determine if a write cycle is in progress. When the write

cycle is completed, the write enable latch is reset.

FIGURE 6-8:

EEPROM READ SEQUENCE

Note:

EEPROM write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page size’) and end at addresses that

are integer multiples of page size – 1. If an

EEWRITE command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page as might be

expected. It is therefore necessary for the

application software to prevent EEPROM

write operations that would attempt to

cross a page boundary.

SCK

23456789 10 11

A7 A6 A5 A4

A1 A0

76543210

Data Out

High-Impedance

A3 A2

Address Byte

12 13 14 15 16 17 18 19 20 21 22 23

Instruction

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