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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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L9966 데이터시트(PDF) 53 Page - STMicroelectronics |
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L9966 데이터시트(HTML) 53 Page - STMicroelectronics |
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53 / 122 page  13.3 SPI mode L9966 SPI is implemented as per the following: CPHA = 1 / CPOL = 0 Communication starts with a falling edge on CS; during this phase the SCLK line must be low. With the following rising edges of SCLK line the MISO data is shifted out from the internal shift register while the MOSI data is latched in on the following falling edges. 13.4 Frame definition The FlexInput chip implements a 32 bits in-frame SPI protocol, see the following tables. Table 34. Complete 32 bits frame Instruction Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 Register Address X X X write data or ignored if R/W=0 Z Z 1 0 1 0 1 Register Address (blind echo) read data or previous content of register in case of write 0xFFFF in case of wrong instruction code Table 35. 16 bits instruction word Instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOSI 1 Register Address X X X MISO Z Z 1 0 1 0 1 Register Address (blind echo) L9966 SPI mode DS12459 - Rev 10 page 53/122 |
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