L9966 datasheet(64/122 Pages) STMICROELECTRONICS

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Figure 33. VRS block diagram - Normal operating mode

GADG1101181045PS

To avoid spurious commutations of the zero crossing comparator, a hysteresis mechanism is implemented. L9966

is able to sink a hysteresis current which generates a voltage drop across the external resistors. The voltage

levels related to the hysteresis function shown hereafter are calculated considering an external series resistance

of 10kΩ on VRSP and 10kΩ on VRSN pins.

As reported in Figure 34. Hysteresis application, the Vdiff (VRSP-VRSN) input differential signal exhibits some

steps at each zero crossing:

•

when the output of the zero crossing comparator is high, the hysteresis current is kept OFF;

•

when the output of the zero crossing comparator is low, the hysteresis current is switched ON.

This approach applies the hysteresis current only on the transition HL of the VRS_OUT signal.

Figure 34. Hysteresis application

GADG1101181050PS

The output of the zero crossing comparator can be further processed by a filtering circuit or directly routed to

VRS_OUT.

15.2.1

VRS normal mode configurations

L9966 integrates two main configurable architectures: VRS_A and VRS_B. These architectures are selected in

VRS register, VRS_SEL bit.

L9966

VRS - Normal mode

DS12459 - Rev 10

page 64/122

L9966 데이터시트(PDF) 64 Page - STMicroelectronics