CS47L85 datasheet(40/370 Pages) CIRRUS

부품명	CS47L85

상세설명	Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub

PDF	370 Pages

Scroll/Zoom	100%

제조업체	CIRRUS [Cirrus Logic]

홈페이지	http://www.cirrus.com

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40 / 370 page

CS47L85

Rev 4.3

4-WIRE (SPI) CONTROL MODE

(input)

SCLK

(input)

MOSI

(input)

tSSU

tSCH

tSCL

tSCY

tDHO

tDSU

tSHO

Figure 9 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle)

SCLK

(input)

MISO

(output)

tDL

(input)

Figure 10 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle)

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

¯¯ falling edge to SCLK rising edge

tSSU

2.6

SCLK falling edge to SS

¯¯ rising edge

tSHO

SCLK pulse cycle time

SYSCLK disabled

(SYSCLK_ENA=0)

tSCY

50.0

SYSCLK_ENA=1 and

SYSCLK_FREQ = 000

76.8

SYSCLK_ENA=1 and

SYSCLK_FREQ > 000

38.4

SCLK pulse width low

tSCL

15.3

SCLK pulse width high

tSCH

15.3

MOSI to SCLK set-up time

tDSU

1.5

MOSI to SCLK hold time

tDHO

1.7

SCLK falling edge to

MISO transition

SCLK slew (90% to 10%) = 5ns,

CLOAD (MISO) = 25pF

tDL

12.6

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