CS47L85 datasheet(37/370 Pages) CIRRUS

37 / 370 page

CS47L85

Rev 4.3

DIGITAL AUDIO INTERFACE - SLAVE MODE

BCLK

(input)

LRCLK

(input)

TXDAT

(output)

RXDAT

(input)

tDSU

tDD

tDH

tLRH

tLRSU

tBCH

tBCL

tBCY

Figure 6 Audio Interface Timing - Slave Mode

Note that BCLK and LRCLK inputs can be inverted if required; Figure 6 shows the default, non-inverted polarity.

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing - Slave Mode

AIFnBCLK cycle time

tBCY

AIFnBCLK pulse width high

BCLK as direct SYSCLK or

ASYNCCLK source

tBCH

All other conditions

AIFnBCLK pulse width low

BCLK as direct SYSCLK or

ASYNCCLK source

tBCL

All other conditions

Audio Interface Timing - Slave Mode

CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns.

AIFnLRCLK set-up time to BCLK rising edge

tLRSU

AIFnLRCLK hold time from BCLK rising edge

tLRH

AIFnTXDAT propagation delay from BCLK falling edge

tDD

12.2

AIFnRXDAT set-up time to BCLK rising edge

tDSU

AIFnRXDAT hold time from BCLK rising edge

tDH

Audio Interface Timing - Slave Mode

CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns.

AIFnLRCLK set-up time to BCLK rising edge

tLRSU

AIFnLRCLK hold time from BCLK rising edge

tLRH

AIFnTXDAT propagation delay from BCLK falling edge

tDD

14.2

AIFnRXDAT set-up time to BCLK rising edge

tDSU

AIFnRXDAT hold time from BCLK rising edge

tDH

Audio Interface Timing - Slave Mode, Master LRCLK

AIFnLRCLK propagation delay from BCLK falling edge

CLOAD = 15pF (output pins). BCLK slew (10% to 90%) = 3ns.

tLRD

14.8

AIFnLRCLK propagation delay from BCLK falling edge

CLOAD = 25pF (output pins). BCLK slew (10% to 90%) = 6ns.

15.9

Notes:

The descriptions above assume non-inverted polarity of AIFnBCLK.

When AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must

be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

CS47L85 데이터시트(PDF) 37 Page - Cirrus Logic

CS47L85 데이터시트(HTML) 37 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL