CS47L85 datasheet(74/370 Pages) CIRRUS

74 / 370 page

CS47L85

Rev 4.3

DIGITAL CORE INPUTS

The digital core comprises multiple input paths as illustrated in Figure 23. Any of these inputs may be selected as a source

to the digital mixers or signal processing functions within the CS47L85 digital core.

Note that the outputs from other blocks within the Digital Core may also be selected as input to the digital mixers or signal

processing functions within the CS47L85 digital core. Those input sources, which are not shown in Figure 23, are described

separately in other sections of the “Digital Core” description.

The bracketed numbers in Figure 23,

e.g.,”(10h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The sample rate for the input signal paths is configured using the applicable IN_RATE, AIFn_RATE or SLIMRXn_RATE

register - see Table 22. Note that sample rate conversion is required when routing the input signal paths to any signal chain

that is asynchronous and/or configured for a different sample rate.

Silence (mute) (00h)

AEC1 Loopback (08h)

AEC2 Loopback (09h)

IN1L signal path (10h)

IN1R signal path (11h)

IN2L signal path (12h)

IN2R signal path (13h)

IN3L signal path (14h)

IN3R signal path (15h)

IN4L signal path (16h)

IN4R signal path (17h)

IN5L signal path (18h)

IN5R signal path (19h)

IN6L signal path (1Ah)

IN6R signal path (1Bh)

AIF1 RX1 (20h)

AIF1 RX2 (21h)

AIF1 RX3 (22h)

AIF1 RX4 (23h)

AIF1 RX5 (24h)

AIF1 RX6 (25h)

AIF1 RX7 (26h)

AIF1 RX8 (27h)

AIF2 RX1 (28h)

AIF2 RX2 (29h)

AIF2 RX3 (2Ah)

AIF2 RX4 (2Bh)

AIF2 RX5 (2Ch)

AIF2 RX6 (2Dh)

AIF2 RX7 (2Eh)

AIF2 RX8 (2Fh)

AIF3 RX1 (30h)

AIF3 RX2 (31h)

AIF4 RX1 (34h)

AIF4 RX2 (35h)

SLIMbus RX1 (38h)

SLIMbus RX2 (39h)

SLIMbus RX3 (3Ah)

SLIMbus RX4 (3Bh)

SLIMbus RX5 (3Ch)

SLIMbus RX6 (3Dh)

SLIMbus RX7 (3Eh)

SLIMbus RX8 (3Fh)

Figure 23 Digital Core Inputs

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