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CS47L85 데이터시트(PDF) 35 Page - Cirrus Logic

부품명 CS47L85
상세설명  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 데이터시트(HTML) 35 Page - Cirrus Logic

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CS47L85
Rev 4.3
35
DIGITAL SPEAKER (PDM) INTERFACE TIMING
SPKCLK
(output)
SPKDAT
(output)
tCY
tLH
tRH
tLSU
tRSU
(left data)
(right data)
VOH
VOL
VOL
tr
tf
VOH
Figure 3 Digital Speaker (PDM) Interface Timing - Mode A
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
PDM Audio Interface Timing
SPKCLKn cycle time
tCY
160
163
358
ns
SPKCLKn duty cycle
45
55
%
SPKCLKn rise/fall time (25pF load)
tr, tf
2
8
ns
SPKDATn set-up time to SPKCLKn rising edge (Left channel)
tLSU
30
ns
SPKDATn hold time from SPKCLKn rising edge (Left channel)
tLH
30
ns
SPKDATn set-up time to SPKCLKn falling edge (Right channel)
tRSU
30
ns
SPKDATn hold time from SPKCLKn falling edge (Right channel)
tRH
30
ns
(right data)
(left data)
VOL
tf
SPKCLK
(output)
SPKDAT
(output)
tLDIS
tRDIS
tLEN
tCY
tREN
VOL
tr
VOH
VOH
Figure 4 Digital Speaker (PDM) Interface Timing - Mode B
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
PDM Audio Interface Timing
SPKCLKn cycle time
tCY
160
163
358
ns
SPKCLKn duty cycle
45
55
%
SPKCLKn rise/fall time (25pF load)
tr, tf
2
8
ns
SPKDATn enable from SPKCLK rising edge (Right channel)
tREN
15
ns
SPKDATn disable to SPKCLK falling edge (Right channel)
tRDIS
5
ns
SPKDATn enable from SPKCLK falling edge (Left channel)
tLEN
15
ns
SPKDATn disable to SPKCLK rising edge (Left channel)
tLDIS
5
ns



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