XIO2000 datasheet(94/150 Pages) TI

94 / 150 page

Classic PCI Configuration Space

November 2005

SCPS097B

4.71 Arbiter Time-Out Status Register

The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out

status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value.

See Table 4−45 for a complete description of the register contents.

PCI register offset:

DEh

Read/Clear

Default value:

00h

BIT NUMBER

RESET STATE

Table 4−45. Arbiter Time-Out Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:6

RSVD

Reserved. Returns 00b when read.

REQ5_TO

RCU

Request 5 time-out status

0 = No time-out

1 = Time-out has occurred

REQ4_TO

RCU

Request 4 time-out status

0 = No time-out

1 = Time-out has occurred

REQ3_TO

RCU

Request 3 time-out status

0 = No time-out

1 = Time-out has occurred

REQ2_TO

RCU

Request 2 time-out status

0 = No time-out

1 = Time-out has occurred

REQ1_TO

RCU

Request 1 time-out status

0 = No time-out

1 = Time-out has occurred

REQ0_TO

RCU

Request 0 time-out status

0 = No time-out

1 = Time-out has occurred

NOTE: If bit 6 (AUTO_MASK) in the arbiter request mask register (offset DDh, see

Section 4.70) is asserted and a PCI bus request time-out is detected, then the request time-out

status bits require a special reset sequence. First, the AUTO_MASK bit must be cleared to

0b. Then, the REQ[5:0]_TO bit will clear after a write-back of 1b.

XIO2000 데이터시트(PDF) 94 Page - Texas Instruments

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