ES9218P datasheet(32/101 Pages) ESS

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ES9218P Datasheet

December 6, 2018

CONFIDENTIAL ADVANCE INFORMATION 1.8

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Start

Stop

Figure 7. I2C Control Interface

Parameter

Symbol

CLK

Constraint

Standard-Mode

Fast-Mode

Unit

MIN

MAX

MIN

MAX

SCL Clock Frequency

fSCL

< CLK/20

100

400

kHz

START condition hold time

tHD,STA

4.0

0.6

s

LOW period of SCL

tLOW

>10/CLK

4.7

1.3

s

HIGH period of SCL (>10/CLK)

tHIGH

>10/CLK

4.0

0.6

s

START condition setup time (repeat)

tSU,STA

4.7

0.6

s

SDA hold time from SCL falling

All except NACK read

NACK read only

tHD,DAT

2/CLK

s

SDA setup time from SCL rising

tSU,DAT

250

100

Rise time of SDA and SCL

1000

300

Fall time of SDA and SCL

300

STOP condition setup time

tSU,STO

0.6

s

Bus free time between transmissions

tBUF

4.7

1.3

s

Capacitive load for each bus line

400

The I2C master clock is affected by the clock gearing. If the auto clock gearing lowers CLK by too much it can cause I2C transactions to fail. See

CLK Requirement

t(SCL high) >=10*t(Clock Gear(CLK))

t(SCL low) >=10*t(Clock Gear(CLK))

The system must ensure this condition can still be met when enabling automatic clock gearing. If the criterion cannot be met for all clock gear

settings, then the clock gearing must be limited using Register 29: GPIO Inversion & Automatic Clock Gearing (0x1D).

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