ES9218P datasheet(63/101 Pages) ESS

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ES9218P Datasheet

CONFIDENTIAL ADVANCE INFORMATION 1.8

December 6, 2018

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Bits

[7:6]

[5:3]

[2]

[1:0]

Mnemonic

invert_gpio

reserved

auto_clk_gear

max_clk_gear

Default

2’b00

3’b000

1’b0

2’b00

Bit

Mnemonic

Description

[7:6]

invert_gpio

Allows each GPIO output to be inverted independently.

•

2’b00: normal GPIO operation (default)

•

2’b01: invert GPIO1 output only

•

2’b10: invert GPIO2 output only

•

2’b11: invert both GPIO outputs

[5:3]

reserved

[2]

auto_clk_gear

Decrease/increase the system clock by automatically adjusting the clock gear setting when the

clocking requirements reach a programmable threshold. This saves power when running at lower

sample rates.

•

1’b0: automatic clock gearing is disabled (default)

•

1’b1: automatic clock gearing is enabled

See Register 49-51: Automatic Clock Gearing Thresholds (0x31 – 0x33) for threshold setting.

[1:0]

max_clk_gear

Sets the maximum allowed divisor (/1, /2, /4, /8) of the system clock that the automatic clock gearing

circuitry can implement. This is useful when running at slow clock rates where a clock gear could slow

the CLK down below the I2C programming constraints.

•

2’b00: sets MCLK/1 as the maximum clock gearing ratio (effectively disabling the automatic

clock gearing) (default)

•

2’b01: sets MCLK/2 as the maximum clock gearing ratio

•

2’b10: sets MCLK/4 as the maximum clock gearing ratio

•

2’b11: sets MCLK/8 as the maximum clock gearing ratio

See Serial Control Interface for I2C clock requirements.

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