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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ES9218P 데이터시트(PDF) 73 Page - ESS Technology,Inc |
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ES9218P 데이터시트(HTML) 73 Page - ESS Technology,Inc |
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73 / 101 page  ES9218P Datasheet CONFIDENTIAL ADVANCE INFORMATION 1.8 December 6, 2018 73 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801 Register 45: Analog Control Override (0x2D) Bits [7] [6] [5] [4] [3] [2] [1] [0] Mnemonic enaux areg_pdb enhpa cph_ens cph_enw apdb cp_clk_sel reserved Default 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 1’b0 Bit Mnemonic Description [7] enaux Sets the state of the output switch when the digital core has taken control of the switch. The switch can be controlled by the digital by setting ENAUX_OE to 1’b1. • 1’b0: switch is disengaged, allowing the DAC and headphone amplifier to drive the output (default) • 1’b1: switch is engaged, allowing the auxiliary input to drive the output Note: The switch should not be engaged when the headphone amplifier is enabled. [6] areg_pdb Enables the analog regulator, which uses the reference voltage enabled by the apdb signal. • 1’b0: analog regulator is disabled (default) • 1’b1: analog regulator is enabled. Note: apdb must be set to 1’b1 for the analog regulator to work correctly [5] enhpa Enables the pre-amplifier for the headphone amplifier. • 1’b0: pre-amplifier is disabled (default) • 1’b1: pre-amplifier is enabled. [4] cph_ens Enables the main charge pump and places it into strong mode. The main charge pump powers the output stage of the headphone amplifier. • 1’b0: main charge pump (strong mode) is disabled (default) • 1’b1: main charge pump (strong mode) is enabled • Note: encp_oe must be set to 1’b1 for the digital core to control the charge pump [3] cph_enw Enables the main charge pump and places it into weak mode. The main charge pump powers the output stage of the headphone amplifier. • 1’b0: main charge pump is disabled (default) • 1’b1: main charge pump is enabled • Note: encp_oe must be set to 1’b1 for the digital core to control the charge pump [2] apdb Enables the analog reference voltage, which is derived by a bandgap. • 1’b0: analog reference is disabled (default) • 1’b1: analog reference is enabled, which supplies a reference voltage for the analog regulator. This bit must be set prior to enabling the analog regulator (AREG_PDB) [1] cp_clk_sel Disables the internal oscillator for the charge pump and uses a digitally generated clock signal instead. The digitally generated clock signal can be configured via register 30-31. • 1’b0: use the internal oscillator as the charge pump clock (default) • 1’b1: use the digitally generated clock as the charge pump clock [0] reserved |
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