NRF9160-SIBA-R datasheet(57/400 Pages) NORDIC

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Power and clock management

5.1.5.4 Soft reset

A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register

(AIRCR register) in the ARM core is set.

5.1.5.5 Watchdog reset

A watchdog reset is generated when the watchdog timer (WDT) times out.

See WDT — Watchdog timer on page 354 chapter for more information.

5.1.5.6 Brownout reset

The brownout reset generator puts the system in reset state if the supply voltage drops below the

brownout reset threshold.

5.1.5.7 Retained registers

A retained register is a register that will retain its value in System OFF mode, and through a reset

depending on reset source. See individual peripheral chapters for information of which registers are

retained for the different peripherals.

5.1.5.8 Reset behavior

Reset behavior depends on the reset source.

The reset behavior is summarized in the table below.

Reset target

Reset source

CPU

Modem

Debug3

SWJ-DP

Not retained

RAM4

Retained

RAM4

WDT

RESETREAS

CPU lockup 5

Soft reset

Wakeup from System OFF

mode reset

x 6

Watchdog reset 7

Pin reset

Brownout reset

Power-on reset

Table 17: Reset behavior for the main components

Note: The RAM is never reset but its content may be corrupted after reset in the cases given in the

table above.

3 All debug components excluding SWJ-DP. See Overview on page 369 chapter for more information

about the different debug components in the system.

4 RAM can be configured to be retained using registers in VMC — Volatile memory controller on page

5 Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible

in System OFF.

6 The debug components will not be reset if the device is in debug interface mode.

7 Watchdog reset is not available in System OFF.

4418_1315 v2.0

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