ST7LUS5 datasheet(33/124 Pages) STMICROELECTRONICS

33 / 124 page

ST7LUS5, ST7LU05, ST7LU09

Supply, reset and clock management

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6.3

Reset sequence manager (RSM)

6.3.1

Introduction

The reset sequence manager includes three RESET sources as shown in Figure 11:

●

External RESET source pulse

●

Internal LVD RESET (Low Voltage Detection)

●

Internal WATCHDOG RESET

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Figure 11.

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic RESET sequence consists of three phases as shown in Figure 10:

●

Active Phase depending on the RESET source

●

64 CPU clock cycle delay

●

RESET vector fetch

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 64 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery

has taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 10.

RESET sequence phases

Figure 11.

Reset block diagram

See Illegal opcode reset on page 87 for more details on illegal opcode reset conditions

RESET

ACTIVE PHASE

INTERNAL RESET

64 CLOCK CYCLES

FETCH

VECTOR

RESET

RON

VDD

INTERNAL

RESET

FILTER

PULSE

GENERATOR

LVD RESET

WATCHDOG RESET

ILLEGAL OPCODE RESET(1)

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