ST20-GP6 datasheet(33/123 Pages) STMICROELECTRONICS

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ST20-GP6

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5.5

Restrictions on interrupt handlers

There are various restrictions that must be placed on interrupt handlers to ensure that they interact

correctly with the rest of the process model implemented in the CPU.

Interrupt handlers must not deschedule.

Interrupt handlers must not execute communication instructions. However they may com-

municate with other processes through shared variables using the semaphore

signal to

synchronize.

Interrupt handlers must not perform 2d block move instructions.

Interrupt handlers must not cause program traps. However they may be trapped by a

scheduler trap.

5.6

Interrupt conﬁguration registers

The interrupt controller is allocated a 4k block of memory in the internal peripheral address space.

Information on interrupts is stored in registers as detailed in the following section. The registers can

be examined and set by the

devlw (device load word) and devsw (device store word) instructions.

Note, they can not be accessed using memory instructions.

HandlerWptr register

The

HandlerWptr registers (1 per interrupt) contain a pointer to the workspace of the interrupt han-

dler. It also contains the

Priority bit which determines whether the interrupt is at a higher or lower

priority than the high priority process queue.

Note, before the interrupt is enabled, by writinga1inthe

Mask register, the user (or toolset) must

ensure that there is a valid

Wptr in the register.

HandlerWptr

Interrupt controller base address + #00 to #1C

Read/Write

Bit

Bit ﬁeld

Function

Priority

Sets the priority of the interrupt. If this bit is set to 0, the interrupt is a higher priority

than the high priority process queue, if this bit is 1, the interrupt is a lower priority

than the high priority process queue.

high priority

low priority

31:2

HandlerWptr

Pointer to the workspace of the interrupt handler.

Reserved, write 0.

Table 5.1

HandlerWptr register format - one register per interrupt

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