HC05V7GRSSLASHD datasheet(131/170 Pages) NXP

131 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 117

MC68HC05V7 Specification Rev. 1.0

15.5.3.1

Logic "0"

A logic zero is defined as either an active to passive transition followed by a passive period

µs in length, or a passive to active transition followed by an active period 128 µs in length

(Figure 15-11(a)).

15.5.3.2

Logic "1"

A logic one is defined as either an active to passive transition followed by a passive period

128

µs in length, or a passive to active transition followed by an active period 64 µs in length

(Figure 15-11(b)).

15.5.3.3

SOF - Start of Frame Symbol

The SOF symbol is defined as a passive to active transition followed by an active period

200

µs in length (Figure 15-11(c)). This allows the data bytes that follow the SOF symbol

to begin with a passive bit, regardless of whether it is a logic one or a logic zero.

15.5.3.4

EOD - End of Data Symbol

The EOD symbol is defined as an active to passive transition followed by a passive period

200

µs in length (Figure 15-11(d)).

15.5.3.5

EOF - End of Frame Symbol

The EOF symbol is defined as an active to passive transition followed by a passive period

of at least 280

µs in length (Figure 15-11(e)). If there is no IFR byte transmitted after an

EOD symbol is transmitted, after another 80

µs the EOD becomes an EOF, indicating the

completion of the message.

15.5.3.6

IFS - Inter-Frame Separation Symbol

The IFS symbol is defined as a passive period 300

µs in length. The IFS symbol contains

no transition, since when used it always follows an EOF symbol.

15.5.3.7

BREAK - Break Signal

The BREAK signal is defined as a passive to active transition followed by an active period

of at least 280

µs (Figure 15-11(f)).

15.5.4

J1850 VPW VALID/INVALID BITS & SYMBOLS

The timing tolerances for receiving data bits and symbols from the J1850 bus have been

defined to allow for variations in oscillator frequencies. In many cases the maximum time

allowed to define a data bit or symbol is equal to the minimum time allowed to define

another data bit or symbol.

Since the minimum resolution of the MDLC for determining what symbol is being received

is equal to a single period of the MUX Interface clock (t

MDLC), an apparent separation in

these maximum time/minimum time concurrences equal to one cycle of t

MDLC occurs.

This one clock resolution allows the MDLC to properly differentiate between the different

bits and symbols, without reducing the valid window for receiving bits and symbols from

transmitters onto the J1850 bus having varying oscillator frequencies.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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