HC05V7GRSSLASHD datasheet(13/170 Pages) NXP

13 / 170 page

Page xiii

MC68HC05V7 Specification Rev. 1.0

LIST OF TABLES

Table 3-1:

Erase Mode Select ..............................................................................22

Table 3-2:

EEPROM Write/Erase Cycle Reduction ..............................................23

Table 5-1:

Vector Address for Interrupts and Reset .............................................29

Table 6-1:

COP Watchdog Timer Recommendations ..........................................43

Table 10-1:

A/D Channel Assignments...................................................................67

Table 12-1:

RTI and COP Rates at 2.1 MHz ..........................................................77

Table 13-1:

PWM Clock Rate .................................................................................81

Table 15-1:

MDLC Transmit Abort Function Summary...........................................97

Table 15-2:

MDLC Rate Selection ..........................................................................98

Table 15-3:

MDLC J1850 Bus Error Summary .....................................................111

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