HC05V7GRSSLASHD datasheet(38/170 Pages) NXP

38 / 170 page

SECTION 3: EPROM and EEPROM

Page 24

MC68HC05V7 Specification Rev. 1.0

BSET

CPEN,PROG

TURN ON CHARGE PUMP

BSET

LATCH,PROG

ENABLE LATCH BIT

BCLR

ER1,PROG

ENSURE PROGRAM (NOT ERASE)

BCLR

ER0,PROG

ENSURE PROGRAM (NOT ERASE)

LDA

#SUMPIN

GET DATA

STA

EESTART

BSET

EEPGM, PROG

ENABLE PROGRAMMING POWER

JSR

DELAY

WAIT FOR PROGRAM TIME

BCLR

EEPGM,PROG

CLEAR EEPGM

JSR

DELAY

WAIT FOR PROG VOLTAGE TO FALL

BCLR

LATCH,PROG

CLEAR LATCH

BCLR

CPEN,PROG

DISABLE CHARGE PUMP

LDA

#SUMPIN

CMP

EESTART

VERIFY

BNE

OUT1

CLC

CLEAR CARRY BIT FOR NO ERROR

OUT

RTS

OUT1

SEC

FLAG AN ERROR

RTS

* THIS ROUTINE GIVES ABOUT A 10 MS DELAY FOR A 2.1Mhz BUS.

* THE SAME DELAY ROUTINE IS USED IN THIS EXAMPLE FOR SIMPLICITY,

* USING THE LONGEST DELAY TIME. USERS WILL WANT TO WRITE SHORTER

* DELAY ROUTINES FOR APPLICATIONS IN WHICH SPEED IS IMPORTANT.

DELAY

EQU

LDA

TCNTH

READ MS BYTE OF TIMER COUNTER

ADD

#$15

ADD OFFSET

STA

TCMPH

STORE BACK IN O/P COMPARE MS BYTE

LDA

TCNTL

READ LS BYTE OF TCR

STA

TCMPL

STORE INTO O/P COMPARE LS BYTE

BRCLR

OCF,TSR,*

WAIT FOR OCF FLAG TO OCCUR

RTS

3.2

OPERATION IN STOP AND WAIT

The RC oscillator for the EEPROM is automatically disabled when entering STOP mode.

The user may want to ensure that the RC oscillator is disabled before entering WAIT mode

to help conserve power.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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