HC05V7GRSSLASHD datasheet(48/170 Pages) NXP

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SECTION 5: INTERRUPTS

Page 34

MC68HC05V7 Specification Rev. 1.0

IRQ latch output can activate an IRQF ﬂag which creates an interrupt request to the CPU

to generate the external interrupt sequence.

When edge sensitivity is selected for the IRQ interrupt, it is sensitive to the following cases:

•

Falling edge on the IRQ pin.

•

Falling edge on any Port A or Port C pin with IRQ enabled.

If the LEVEL option selected, the active low state of the IRQ pin can also activate an IRQF

flag, which creates an IRQ request to the CPU to generate the IRQ interrupt sequence.

When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to the

following cases:

•

Low level on the IRQ pin.

•

Falling edge on the IRQ pin.

•

Falling edge on any Port A or Port C pin with IRQ enabled.

The IRQE enable bit controls whether an active IRQF flag (IRQ pin interrupt) can generate

an IRQ interrupt sequence. The IRQPAE enable bit controls whether an active IRQPAF flag

(Port A interrupt) can generate an IRQ interrupt sequence. The IRQPCE enable bit controls

whether an active IRQPCF flag (Port C interrupt) can generate an IRQ interrupt sequence.

The IRQ interrupt is serviced by the interrupt service routine located at the address

specified by the contents of $3FFA and $3FFB.

The IRQF latch is automatically cleared by entering the interrupt service routine to maintain

compatibility with existing M6805 interrupt servicing protocol. To allow the user to identify

the source of the interrupt, the port interrupt flags (IRQPAF and IRQPCF) are not cleared

automatically. These flags must be cleared within the interrupt handler prior to exit in order

to prevent repeated re-entry. This is achieved by writing a logic one to the IRQA (IRQ

acknowledge) bit, which will clear all pending IRQ interrupts (including a pending IRQ pin

interrupt).

The interrupt request flags (IRQPAF and IRQPCF) are read only and cannot be cleared by

writing to them. The acknowledge flag always reads as a logic 0. Together, these features

permit the safe use of read-modify-write instructions (for example, BSET, BCLR) on the

ICSR.

NOTE:

Although read modify write instruction use is allowable on the ICSR, shift

operations should be avoided due to the possibility of inadvertently setting

the IRQA.

5.5.1

IRQ CONTROL/STATUS REGISTER (ICSR) $1F

The IRQ interrupt function is controlled by the ICSR located at $001F. All unused bits in the

ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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