HC05V7GRSSLASHD datasheet(113/170 Pages) NXP

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SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 99

MC68HC05V7 Specification Rev. 1.0

15.2.3

MDLC STATUS REGISTER (MSR) $0F

This register indicates the transmit and receive status of the MDLC.

All bits may be read in all modes of MCU operation.

Bits 0,1, 4, 5, 6, and 7 will always read as zeros and can never be written to.

Bits 2 and 3 are reflective of CPU interrupt request signals and are asserted as long as their

respective CPU interrupt request is pending. Neither bit is affected by CPU interrupt

requests generated when the MDLC ’wakes up’ from MDLC Stop or MDLC Wait mode.

All writes to this register are ignored in all modes of MCU operation.

15.2.3.1

TXMS - Transmitted Message Successfully

When set this bit indicates that the Tx Buffer contents have been sent successfully.

An access of the Tx Control Register (MTCR) will clear this bit.

15.2.3.2

RXMS - Received Message Successfully

When set, this bit indicates that one of the Rx Buffers contains a new message.

This bit can only be cleared if both Rx Buffers are empty. If only one message has been

received into an Rx Buffer by the MDLC, any access (read or write) of the MDLC Rx Status

If a second message is received after the RXMS bit has been cleared by the CPU as it is

retrieving the first message, the RXMS bit will immediately be set again, and will remain set

until the MRSR is accessed once the last message received is made available to the CPU.

If both Rx Buffers contain a received message, the RXMS bit will simply remain set until the

MRSR register is accessed once the last message received is made available to the CPU.

15.2.3.3

TXMS and RXMS Interrupts

If either the TXMS or the RXMS bit is set, and if interrupts are enabled, an interrupt request

will be made to the CPU. The interrupt service routine may poll these bits to establish the

cause of the interrupt. The mechanism for clearing each of these bits will also clear the

associated CPU interrupt request.

Alternatively, if interrupts are disabled, the CPU may poll these bits periodically to see if a

change in status has occurred.

Figure 15-4:

MDLC Status Register (MSR)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

RXMS

TXMS

RESET

00000000

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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