M58LR128FT datasheet(31/82 Pages) STMICROELECTRONICS

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M58LR128FT, M58LR128FB

quence can be suspended and resumed as often

as required as long as the operating conditions of

the device are met.

A Synchronous Burst Read operation is suspend-

ed when Chip Enable, E, is Low and the current

address has been latched (on a Latch Enable ris-

ing edge or on a valid clock edge). The Clock sig-

nal is then halted at VIH or at VIL, and Output

Enable, G, goes High.

When Output Enable, G, becomes Low again and

the Clock signal restarts, the Synchronous Burst

Read operation is resumed exactly where it

stopped.

WAIT will revert to high-impedance when Output

Enable, G, or Chip Enable, E, goes High.

See Table 22., Synchronous Read AC Character-

istics, and Figure 14., Synchronous Burst Read

Suspend AC Waveforms, for details.

Single Synchronous Read Mode

Single Synchronous Read operations are similar

to Synchronous Burst Read operations except that

the memory outputs the same data to the end of

the operation.

Synchronous Single Reads are used to read the

Electronic Signature, Status Register, CFI, Block

Protection Status, Configuration Register Status

or Protection Register. When the addressed bank

is in Read CFI, Read Status Register or Read

Electronic Signature mode, the WAIT signal is as-

serted during the X latency, the Wait state and at

the end of a 4, 8 and 16 Word burst. It is only deas-

serted when output data are valid.

See Table 22., Synchronous Read AC Character-

istics, and Figure 12., Synchronous Burst Read

AC Waveforms, for details.

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