AT25QL641 datasheet(32/80 Pages) RENESAS

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DS-AT25QL641-130 Rev. G

Page 32

Sep 14, 2022

AT25QL641 Datasheet

8.13 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O command reduces cycle overhead through double access using two I/O pins: I/O0 and

I/O1.

Continuous Read Mode

The Fast Read Dual I/O command can further reduce cycle overhead through setting the Mode bits (M7-0)

after the input Address bits (A23-0). The upper nibble of the Mode (M7-4) controls the length of the next Fast

Read Dual I/O command through the inclusion or exclusion of the first byte command code. The lower nibble bits

of the Mode (M3-0) are don’t care (X), However, the I/O pins should be high-impedance prior to the falling edge

of the first data out clock.

If the Mode bits (M7-0) equal Ax hex, then the next Fast Dual I/O command (after CS is raised and then lowered)

does not require the command (BBh) code, as shown in Figure 20 and Figure 21. This reduces the command

sequence by eight clocks and allows the address to be immediately entered after CS is asserted low. If Mode

bits (M7-0) are any value other Ax hex, the next command (after CS is raised and then lowered) requires the first

byte command code, thus returning to normal operation. A mode bit reset can be used to reset t h e mode bits

(M7-0) before issuing normal commands.

Figure 20. Fast Read Dual I/O Command (initial command or previous M7-0≠ Axh)

36 37

SO(IO

SI(IO

SCK

MSB

420

6420

7531

s switch from

Input to Output

SO (IO

SI (IO

SCK

Command (BBh)

6420

7531

123

Mode 3

Mode 0

A23-16

A15-8

Byte 1

Byte 2

Byte 3

Byte 4

A7-0

M7-0

MSB

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