AT25QL641 datasheet(41/80 Pages) RENESAS

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DS-AT25QL641-130 Rev. G

Page 41

Sep 14, 2022

AT25QL641 Datasheet

8.18 32-kByte Block Erase (52h)

The 32 kB Block Erase command is used for a 32-kByte block erase operation. Prior to the Block Erase

Command, a Write Enable (06h) command must be issued. The command is initiated by driving the CS pin low

and shifting the command code 52h followed b y a 24-bit block address (A23-A0). See Figure 31 and Figure 32

below. The CS pin must go high after the eighth bit of the last byte has been latched in, otherwise the Block Erase

command is not executed. After CS is driven high, the self-timed Block Erase command commences for a time

duration of tBE1 (see Table 26, AC Electrical Characteristics).

While the block erase operation is in progress, the Read Status Register (05h) command may still be used to

read the status of the BUSY bit. The BUSY bit is a 1 during the block erase operation and becomes a 0 when

the cycle is finished and the device is ready to accept other commands again. When the BUSY bit is asserted,

the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 31. 32 kB Block Erase Command (SPI Mode)

Figure 32. 32 kB Block Erase Command (QPI Mode)

246

Mode 3

Mode 0

Mode 3

Mode 0

High-Impedance

SCK

Command (52h)

24-Bit Address

MSB

SCK

Mode 3

Command

52h

A23-16

A15-8

A7-0

Mode 0

Mode 3

Mode 0

MSB

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