RA4E2 datasheet(33/90 Pages) RENESAS

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VCC

RES

Internal reset signal

(low is valid)

tRESWP

tRESWT

VCCmin

Figure 2.12

RES pin input timing under the condition that VCC exceeds VPOR voltage threshold

RES

Internal reset signal

(low is valid)

tRESWD, tRESWS, tRESW

tRESWT

Figure 2.13

Reset input timing

2.3.4

Wakeup Timing

Table 2.20

Timing of recovery from low power modes (1 of 2)

Parameter

Symbol

Min Typ

Max

Unit Test conditions

Recovery time from

Software Standby

mode*1

Crystal resonator

connected to main clock

oscillator

System clock source is

main clock oscillator*2

tSBYMC*13 —

2.1

2.4

Figure 2.14

The division ratio of all

oscillators is 1.

System clock source is

PLL with main clock

oscillator*3

tSBYPC*13 —

2.2

2.6

External clock input to

main clock oscillator

System clock source is

main clock oscillator*4

tSBYEX*13 —

125

μs

System clock source is

PLL with main clock

oscillator*5

tSBYPE*13 —

170

255

μs

System clock source is sub-clock oscillator*6 *11

tSBYSC*13 —

0.7

0.8

System clock source is LOCO*7 *11

tSBYLO*13 —

0.7

0.9

System clock source is HOCO clock oscillator*8

tSBYHO*13 —

130

µs

System clock source is PLL with HOCO*9

tSBYPH*13 —

175

265

µs

System clock source is MOCO clock oscillator*10

tSBYMO*13 —

µs

Recovery time from

Deep Software

Standby mode

DPSBYCR.DEEPCUT[1] = 0 and

DPSWCR.WTSTS[5:0] = 0x0E

tDSBY

—

0.38

0.54

Figure 2.15

DPSBYCR.DEEPCUT[1] = 1 and

DPSWCR.WTSTS[5:0] = 0x19

tDSBY

—

0.55

0.73

Wait time after cancellation of Deep Software Standby mode

tDSBYWT

—

tcyc

RA4E2 Datasheet

2. Electrical Characteristics

R01DS0413EJ0110 Rev.1.10

Feb 28, 2023

Page 33 of 90

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