전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

RA4E2 데이터시트(PDF) 52 Page - Renesas Technology Corp

부품명 RA4E2
상세설명  Renesas Microcontrollers
PDF  90 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RA4E2 데이터시트(HTML) 52 Page - Renesas Technology Corp

Back Button RA4E2 Datasheet HTML 48Page - Renesas Technology Corp RA4E2 Datasheet HTML 49Page - Renesas Technology Corp RA4E2 Datasheet HTML 50Page - Renesas Technology Corp RA4E2 Datasheet HTML 51Page - Renesas Technology Corp RA4E2 Datasheet HTML 52Page - Renesas Technology Corp RA4E2 Datasheet HTML 53Page - Renesas Technology Corp RA4E2 Datasheet HTML 54Page - Renesas Technology Corp RA4E2 Datasheet HTML 55Page - Renesas Technology Corp RA4E2 Datasheet HTML 56Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 52 / 90 page
background image
Table 2.30
IIC timing(1)-3
Setting of the SDA0_D, SCL0_D pins is not required with the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
Unit
IIC
(Fast-mode+)
BFCTL.FMPE = 1
SCL input cycle time
tSCL
10(18) × tI3Ccyc + 240
ns
SCL input high pulse width
tSCLH
5(9) × tI3Ccyc + 120
ns
SCL input low pulse width
tSCLL
5(9) × tI3Ccyc + 120
ns
SCL, SDA rise time
tSr
120
ns
SCL, SDA fall time
tSf
20 × (external pullup voltage/5.5
V)
120
ns
SCL, SDA input spike pulse removal
time
tSP
0
1(4) × tI3Ccyc
ns
SDA input bus free time when
wakeup function is disabled
tBUF
5(9) × tI3Ccyc + 120
ns
SDA input bus free time when
wakeup function is enabled
tBUF
5(9) × tI3Ccyc + 4 × tTcyc + 120
ns
START condition input hold time
when wakeup function is disabled
tSTAH
tI3Ccyc + 120
ns
START condition input hold time
when wakeup function is enabled
tSTAH
1(5) × tI3Ccyc + tTcyc + 120
ns
Restart condition input setup time
tSTAS
120
ns
Stop condition input setup time
tSTOS
120
ns
Data input setup time
tSDAS
tI3Ccyc + 30
ns
Data input hold time
tSDAH
0
ns
SCL, SDA capacitive load
Cb*1
550
pF
Note:
tI3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle.
Note:
Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1.
Note 1. Cb indicates the total capacity of the bus line.
SDAn
SCLn
VIH
VIL
tSTAH
tSCLH
tSCLL
P*1
S*1
tSf
tSr
tSCL
tSDAH
tSDAS
tSTAS
tSP
tSTOS
P*1
tBUF
Sr*1
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.41
I2C bus interface input/output timing
RA4E2 Datasheet
2. Electrical Characteristics
R01DS0413EJ0110 Rev.1.10
Feb 28, 2023
Page 52 of 90



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com