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RA4E2 데이터시트(PDF) 37 Page - Renesas Technology Corp

부품명 RA4E2
상세설명  Renesas Microcontrollers
PDF  90 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
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Note:
200 ns minimum in Software Standby mode.
Note:
If the clock source is switched, add 4 clock cycles of the switched source.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock.
tNMIW
NMI
Figure 2.17
NMI interrupt input timing
tIRQW
IRQ
Figure 2.18
IRQ interrupt input timing
2.3.6
I/O Ports, POEG, GPT, AGT, and ADC12 Trigger Timing
Table 2.22
I/O ports, POEG, GPT, AGT, and ADC12 trigger timing
GPT16E Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
Unit
Test conditions
I/O ports
Input data pulse width
tPRW
1.5
tPcyc
Figure 2.19
POEG
POEG input trigger pulse width
tPOEW
3
tPcyc
Figure 2.20
GPT
Input capture pulse width
Single edge
tGTICW
1.5
tPDcyc
Figure 2.21
Dual edge
2.5
GTIOCxY output skew
(x = 0, 1, Y = A or B)
Middle drive buffer
tGTISK*1
4
ns
Figure 2.22
High drive buffer
4
GTIOCxY output skew
(x = 4, 5, Y = A or B)
Middle drive buffer
4
High drive buffer
4
GTIOCxY output skew
(x = 0, 1, 4, 5, Y = A or B)
Middle drive buffer
6
High drive buffer
6
OPS output skew
GTOUUP, GTOULO, GTOVUP,
GTOVLO, GTOWUP, GTOWLO
tGTOSK
5
ns
Figure 2.23
AGT
AGTIO, AGTEE input cycle
tACYC*2
100
ns
Figure 2.24
AGTIO, AGTEE input high width, low width
tACKWH, tACKWL
40
ns
AGTIO, AGTO, AGTOA, AGTOB output cycle
tACYC2
62.5
ns
ADC12
ADC12 trigger input pulse width
tTRGW
1.5
tPcyc
Figure 2.25
Note:
tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.
Note 2. Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
RA4E2 Datasheet
2. Electrical Characteristics
R01DS0413EJ0110 Rev.1.10
Feb 28, 2023
Page 37 of 90



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