RA4E2 datasheet(55/90 Pages) RENESAS

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Table 2.33

I3C timing (push-pull timing parameters for SDR mode)

Conditions: VCC = 3.00 to 3.60 V

Setting of the I3C_SDA, I3C_SCL pins is not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test

conditions

I3C Push-Pull Timing

Parameters for SDR Mode

SCL Clock Frequency

fSCL*1

0.01

12.5

MHz

—

SCL Clock Low Period

tLOW

—

Figure 2.43

tDIG_L*2 *4

—

Figure 2.43

SCL Clock High Period for

Mixed Bus

tHIGH_MIXED

—

Figure 2.43

tDIG_H_MIXED*2

Figure 2.43

SCL Clock High Period

tHIGH

—

Figure 2.43

tDIG_H*2

—

Figure 2.43

Clock in to Data Out for Slave tSCO

—

Figure 2.48

SCL Clock Rise Time

tCR

—

150 × 1 /fSCL (capped

at 60)

Figure 2.43

SCL Clock Fall Time

tCF

—

150 × 1 /fSCL (capped

at 60)

µs

Figure 2.43

SDA Signal Data

Hold in Push-Pull

Mode

Master tHD_PP*4

tCR + 3 and

tCF + 3

—

Figure 2.47

Slave

tHD_PP

—

Figure 2.47

SDA Signal Data Setup in

Push-Pull Mode

tSU_PP

N/A

Figure 2.49

Clock After Repeated START

(Sr)

tCASr

tCASmin

N/A

Figure 2.50

Clock Before Repeated

START (Sr)

tCBSr

tCASmin / 2

N/A

Figure 2.50

Capacitive Load per Bus Line

(SDA/SCL)

—

Note 1. fSCL = 1 / (tDIG_L + tDIG_H)

Note 2. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH.

Note 3. When communicating with an I3C Device on a mixed Bus, the tDIG_H_MIXED period must be constrained in order to make sure that

I2C Devices do not interpret I3C signaling as valid I2C signaling.

Note 4. As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks, and tCR + 3

for rising edge clocks.

RA4E2 Datasheet

2. Electrical Characteristics

R01DS0413EJ0110 Rev.1.10

Feb 28, 2023

Page 55 of 90

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