DSP56600FMSLASHAD datasheet(22/76 Pages) NXP

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Preliminary

1-16

DSP56652 Technical Data Sheet

MOTOROLA

Pin and Signal Descriptions

DSP56652 Signal Description

Chip Selects

Table 1-10

Chip Select Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

CS0

Output

Chip-

driven

Chip select 0Ñ

This signal is asserted low based on the decode of the

internal address bus bits A[31:24] and is typically used as the external

flash memory chip select. After reset, accesses using this CS have a

default of 15 wait states.

CS1ÐCS4

Output

Driven

high

Chip select 1Ðchip select 4Ñ

These signals are asserted low based

on the decode of the internal address bus bits A[31:24] of the access

address.

When not selected as chip select signals, these signals become

general purpose outputs (GPOs). After reset, these signals are

GPOs that are driven high.

CS5

Output

Driven

low

Chip select 5Ñ

This signal is asserted high based on the decode of

the internal address bus bits A[31:24] of the access address.

When not selected as a chip select signal, this signal becomes a

GPO. After reset, this signal is a GPO that is driven low.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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