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FS6407 데이터시트(PDF) 69 Page - NXP Semiconductors

부품명 FS6407
상세설명  Power system basis chip with high speed can transceiver
PDF  111 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6407 데이터시트(HTML) 69 Page - NXP Semiconductors

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NXP Semiconductors
69
FS6407/FS6408
7.3.5
INIT IO_WU2
WU_2_1:0
Description
Wake-up configuration for IO_2
00
NO wake-up capability
01
Wake-up on rising edge only
10
Wake-up on falling edge only
11
Wake-up on any edge
Reset condition
Power On Reset
INT_inh_IO_1
Description
Inhibit the INT pulse for IO_1. IO_1 masked in IO_G. Avoid INT when used in FS
0
INT NOT masked
1INT masked
Reset condition
Power On Reset
INT_inh_IO_0
Description
Inhibit the INT pulse for IO_0. IO_0 masked in IO_G. Avoid INT when used in FS
0
INT NOT masked
1INT masked
Reset condition
Power On Reset
Table 25. INIT IO_WU2 register description
Write
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
1
0
0
0
1
0
1
P
WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0
INT_inh
_IO_23
INT_inh
_IO_45
MISO
SPI_G
WU
CAN_G Reserved
IO_G
Vpre_G
Vcore_
G
Vothers
_G
WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0
INT_inh
_IO_23
INT_inh
_IO_45
Read
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MOSI
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
MISO
SPI_G
WU
CAN_G Reserved
IO_G
Vpre_G
Vcore_
G
Vothers
_G
WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0
INT_inh
_IO_23
INT_inh
_IO_45
Table 26. INIT IO_WU2. Description and configuration of the bits (default value in bold)
WU_3_1:0
Description
Wake-up configuration for IO_3
00
NO wake-up capability
01
Wake-up on rising edge only
10
Wake-up on falling edge only
11
Wake-up on any edge
Reset condition
Power On Reset
Table 24. INIT IO_WU1. Description and configuration of the bits (default value in bold) (continued)



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