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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FS6407 데이터시트(PDF) 88 Page - NXP Semiconductors |
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FS6407 데이터시트(HTML) 88 Page - NXP Semiconductors |
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88 / 111 page  88 NXP Semiconductors FS6407/FS6408 Table 64. INIT SUPERVISOR2. Description and configuration of the bits (default value in bold) Vaux_FS1:0 Description VAUX safety input. 00 No effect of VAUX_OV and VAUX_UV on RSTb and FSxx 01 VAUX_OV DOES HAVE an impact on RSTb and FSxx. VAUX_UV DOES HAVE an impact on RSTb only 10 VAUX_OV DOES HAVE an impact on RSTb and FSxx. No effect of VAUX_UV on RSTb and FSxx 11 Both VAUX_OV and VAUX_UV DO HAVE an impact on RSTb and FSxx Reset condition Power On Reset DIS_8s Description Disable the 8.0 s timer used to enter Deep Fail-safe mode 0 ENABLED 1 DISABLED Reset condition Power On Reset Secure3:0 Description Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 SPI_FS_err Description Secured SPI communication check, concerns fail-safe logic only. 0No error 1 Error detected in the secured bits Reset condition Power On Reset SPI_FS_CLK Description SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset SPI_FS_Req Description Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe Logic only 0No error 1 SPI violation Reset condition Power On Reset SPI_FS_Parity Description SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1Parity bit ERROR Reset condition Power On Reset |
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