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DA9210

DA9210 Multi-Phase 12 A DC-DC Buck

Converter

Company Confidential

Datasheet

Revision 2.3

28-Feb-2022

CFR0011-120-00

57 of 96

10.5.2

2-WIRE Communication

With control IF_TYPE, the DA9210 power manager interface can be configured towards a 2-WIRE

serial data exchange. It has a configurable device write address (default: 0xD0) and a configurable

device read address (default: 0xD1). For details of configurable addresses, see control

IF_BASE_ADDR.

The SK pin provides the 2-WIRE clock (SCL), and SI carries all the power manager bidirectional 2-

WIRE data, (SDA). The 2-WIRE interface is open-drain supporting multiple devices on a single line.

The bus lines require external pull-

up resistors (2 kΩ to 20 kΩ range). The attached devices only

drive the bus lines LOW. As a result, two devices cannot conflict if they drive the bus simultaneously.

In standard/fast mode, the highest frequency of the bus is 400 kHz. The exact frequency can be

determined by the application and does not have any relation to the DA9210 internal clock signals.

DA9210 follows the host clock speed within the described limitations and does not initiate any clock

arbitration or slow down. An automatic reset of the interface can be triggered via control 2WIRE_TO

if the clock signal stops toggling for more than 35 ms (compatible with SMBus).

The interface supports operation compatible with Standard, Fast, Fast-Plus and High Speed modes

of the I2C bus specification Rev 4 (UM10204_4). Operation in high speed mode at 3.4 MHz requires

mode changing in order to change spike suppression and slope control characteristics to be

compatible with the I2C bus specification. The high speed mode can be enabled on a transfer by

transfer basis by sending the master code (0000 1XXX) at the beginning of the transfer. DA9210

does not make use of clock stretching and delivers read data up to 3.4 MHz, without additional delay.

Communication on the 2-WIRE bus always takes place between two devices, one acting as the

master and the other as the slave. The DA9210 only operates as a slave.

Unlike 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register map (up to

256 addresses). The register at address 0x00 on each page is used as a page control register (with

the 2-WIRE bus ignoring the LSB of control REG_PAGE). Writing to the page control register

changes the active page for all subsequent read/write operations, unless an automatic return to page

0 is selected by asserting control REVERT. After modifying the active page, unless REVERT is

asserted, it is recommended to read back the page control register to ensure that future data

exchange accesses the intended registers.

In 2-WIRE operation DA9210 offers an alternative way to access register page 2 and 3. It removes

the need for the preceding page selection writes by increasing the device write/read address by one

(default 0xD2/0xD3) for any direct access of page 2 and 3 (page 0 and 1 access requires the basic

write/read device address with the MSB of REG_PAGE

‘0’).

Details of the 2-WIRE Control Bus Protocol

The following description uses the standard terms SDA for the serial data, pin SI, and SCL for the

serial clock, pin SK.

All data is transmitted across the 2-WIRE bus in 8-bit groups. To send a bit, the SDA line is driven at

the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and

then low. This pulse on SCL stores th

e SDA bit in the receiver’s shift register.

A 2-byte serial protocol is used: one address byte and one data byte. The data and address are

transmitted MSB first for both read and write operations. All transmissions begin with the START

condition from the master, during which the bus is in IDLE state (the bus is free). It is initiated by a

high-to-low transition on the SDA line while the SCL is in high state. A STOP condition is indicated by

a low-to-high transition on the SDA line while the SCL is in high state. The START and STOP

conditions are illustrated in Figure 40.

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