ZAMC4100GA2R datasheet(49/156 Pages) RENESAS

49 / 156 page

ZAMC4100 Datasheet

January 26, 2016

3.6.

SBC Interrupts

Most of the interrupts are generated by the peripherals within SBC and MCU chips. The interrupt organization of

the SBC chip is shown in Figure 3.8. The SBC interrupts are captured by the interrupt controller and after OR-

reduction are propagated to the MCU via IRQN line. The IRQN line is active-low and appears as an external

interrupt input to the MCU.

As shown in Figure 3.8, the interrupt logic has two levels: global interrupts and peripheral interrupts. Each

interrupt source has an individual interrupt enable (IE) and interrupt flag (IF) bit. Some of the IF bits are mapped

to the slave status byte and are shifted out to the MCU whenever a SPI command byte is shifted in to the SBC

(Figure 3.10-D).

The global interrupts are controlled via the IRQCTRL register and read via IRQSTAT (see section 3.6.2). The

peripheral interrupts are grouped by source and functionality and are combined using an OR-function to be a

single global interrupt bit. This allows the MCU to first determine which peripheral is causing an interrupt and then

to check the particular event. For example if the ADCIF interrupt flag bit is set, the reason might be that the ADC

conversion is finished (ADCRDYIF=1) or it might come from the ADC result comparator (ADCCMPIF=1) (see

section 3.7.5).

Figure 3.8 SBC Interrupt Logic Organization

IRQN

IRQSTAT

WDTIF

WDTIE

OVTIF

OVTIE

SEIF

SEIE

ADCIF

ADCIE

HBOCIF

HBOCIE

HSOCIF

HSOCIE

ECMOCIF

ECMOCIE

LINIF

LINIE

SBC

MCU

ZAMC4100

MCU

Interrupt

Controller

IRQCTRL

ADCRDYIF

ADCCMPIF

HB1OCIF

HB2OCIF

HB3OCIF

HB4OCIF

HS1OCIF

HS2OCIF

HS3OCIF

HS4OCIF

LINWUIF

LINDTOIF

LINSHIF

ADCSTAT

HBDSTAT

HSDSTAT

LINSTAT

SBC Global

Interrupts

SBC Peripheral Interrupts

OVIF

UVIF

RSTSTAT

CPVEIF

OSCLEIF

CMPEN

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