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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ZAMC4100GA2R 데이터시트(PDF) 24 Page - Renesas Technology Corp |
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ZAMC4100GA2R 데이터시트(HTML) 24 Page - Renesas Technology Corp |
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24 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 24 January 26, 2016 1.3.3. SPI Bus Timing Refer to Figure 1.2 and Table 1.16 for the definitions of the SPI timing parameters. Table 1.16 ZAMC4100 SPI Bus Timing Parameters Parameter Symbol Min. Typ. Max. Unit SPI clock period 1) tCLK 0.3 - 6.4 µs SPI pulse width tP 40% tCLK 50% tCLK 60% tCLK µs Chip-select setup time 2) tCSNSU 1.0 - - µs Chip-select hold time 2) tCSNHD 1.0 - - µs SPI access time tACC 1.0 2.0 - µs 1) The maximum tCLK value is determined by the maximum value that can be programmed in MCU register Z1_SPICLKCFG[7:2] (see Table 4.23). 2) The parameters tCSNSU and tCSNHD require at least 3 OSCH clock cycles. When oscillator OSCH is not trimmed, it runs at a lower frequency. Figure 1.2 SPI Communication Timing Diagram MOSI SPI_CLK 7 MISO 7 6 0 5 1 7 6 0 5 1 7 6 6 5 1 0 7 6 5 1 0 7 6 tCSNSU tCSNHD tACC tCLK tP CMD/SSB R/W DATA CSN |
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