ST72361 datasheet(188/224 Pages) STMICROELECTRONICS

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ST72361

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CLOCK CHARACTERISTICS (Cont’d)

12.5.4 PLL Characteristics

Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C

1) or V

DD 4.5 to 5.5V @ TA -40 to 125°C

Notes:

1. Data characterized but not tested.

2. Under characterization

Figure 101. PLL Jitter vs Signal Frequency1)

The user must take the PLL jitter into account in

the application (for example in serial communica-

tion or sampling of high frequency signals). The

PLL jitter is a periodic effect, which is integrated

over several CPU cycles. Therefore, the longer the

period of the application signal, the less it is im-

pacted by the PLL jitter.

Figure 101 shows the PLL jitter integrated on ap-

plication signals in the range 125 kHz to 2 MHz. At

frequencies of less than 125 kHz, the jitter is neg-

ligible.

Notes:

1. Measurement conditions: fCPU = 4 MHz, TA = 25°C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(PLL)

PLL Voltage Range

TA = 0 to +70°C

3.8

5.5

TA = -40 to +125°C

4.5

fOSC

PLL input frequency range

MHz

∆ fCPU/fCPU

PLL jitter1)

fOSC = 4 MHz, VDD = 4.5 to 5.5V

Note 2

fOSC = 2 MHz, VDD = 4.5 to 5.5V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

2000

1000

500

250

125

Application Signal Frequency (KHz)

PLL ON

PLL OFF

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