TMPR4955AF datasheet(55/168 Pages) TOSHIBA

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Chapter 3 Initialization Interface

3-5

wait instruction is executed during a bus operation, the Halt mode is after the bus

operation completes.

Write buffer operations do not stop during Halt mode: when the write buffer contain

date, write operations continue until the write buffer empties.

To recover from Halt mode, assert one of the following signal:

Int[5:0]*, NMI*, Reset*, or ColdReset*.

When recovering from Halt mode by asserting a non-enabled Int[5:0]* signal, the

value of the Int Mask field in the Status Register is not affected.

When recovering from Halt mode via the ColdReset* signal, NMI* signal, or an

enabled Int[5:0]* signal, the top instruction of the exception handler corresponding to

the signal is executed. On execution of the top instruction, the EPC points to

instruction following the Wait instruction. When recovering via a non-enabled Int[5:0]*

signal, the processor resumes execution from the instruction following the instruction

used to change to Halt mode.

3.3.2

Operating Modes

The TX4955A has three operating modes, User mode, Supervisor mode and Kernel mode,

that function in both 32- and 64-bit operations. The KSU, EXL and ERL bits in the Status

KSU

EXL

ERL

Mode

—

32-bit addressing for User mode

—

64-bit addressing for User mode

—

32-bit addressing for Supervisor mode

—

64-bit addressing for Supervisor mode

—

32-bit addressing for Kernel mode

—

32-bit addressing for Kernel mode

—

32-bit addressing for Kernel mode

—

64-bit addressing for Kernel mode

—

64-bit addressing for Kernel mode

—

64-bit addressing for Kernel mode

3.3.3

System Endianness

By setting the External pin (Endian), the state of system endianness is provide to the

processor.

Indicateds the initial setting of the endian during a reset.

Endian = 0: Little Endian

Endian = 1: Big Endian

Note: Be bit in the Config register is read only.

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