TMPR4955AF datasheet(72/168 Pages) TOSHIBA

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Chapter 5 Cache Organization

5-12

5.10.3

Instruction Cache Line Replacement

For an instruction cache miss, refill is done using sequential ordering, starting from the

first word of the retrieved cache line.

During an instruction cache miss, a memory read is issued. The requested line is

returned from memory and written to the instruction cache. At this time the pipeline

resumes execution, and the instruction cache is reaccessed.

The replacement sequence for an instruction cache miss is:

1. Move the instruction physical address to the processor pads.

2. Wait for a PClock cycle, aligned with an SClock boundary, to occur.

3. Read the line from memory and write it out to the instruction cache array.

4. Restart the processor pipe.

The instruction cache miss penalties, in number of PClock, is given in Table 5.10.3.

Table 5.10.3 Instruction Cache Refill Penalty Cycle Count

Number of

PClock

Action

Stall the RF stage.

Transfer address to the write buffer and wait for the pipeline start signal.

∼ 2

Transfer to the external SysAD bus.

Time needsd to access memory, measured in PClock cycles.

Transfer the cache line from memory to the SysAD bus.

Transfer the cache line from the external bus to the internal bus.

Restart the RF stage.

5.11 Manipulation of the Caches by an External Agent

The TX4955A does not provide any mechanisms for an external agent to examine and

manipulate the state and contents of the caches.

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