TMPR4955AF datasheet(78/168 Pages) TOSHIBA

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Chapter 6 TX4955A System Interface

6-6

6.2.6

Processor Requests and External Requests

Requests are broadly categorized as processor requests and external requests. This

section will describe these two categories.

When a system event is generated, either a single request or a series of requests (referred

to as processor requests) are issued via the system interface so the processor can access an

external resource and invoke the service for the event. In order for this operation to be

performed properly, the processor system interface must be connected to a system agent

that meets the two following conditions:

1) It is in compliance to the system interface protocol.

2) It can regulate access to system resources.

An external agent that requests access to the processor cache or the status registers

generates an external request. This access request is transferred via the system interface.

Figure 6.2.5 illustrates the system event and request cycles.

Figure 6.2.5 Requests and System Event

6.2.6.1

Rules relating to processor requests

The following rules apply to processor requests.

•

After a processor read request is issued, the processor cannot issue the next

read request until after it receives a read response.

•

When in the R4000 compatible mode, after a write request is issued, at least 4

cycles must pass from when the write request issue cycle is complete until the

processor can issue the next request. This is because two dummy system

cycles are inserted as illustrated in Figure 6.2.6 by consecutive write requests

of single data cycles.

Figure 6.2.6 Timing of Consecutive Write Cycles

System Events

・ Load miss

・ Store miss

・ Store bit

・ Uncached load/store

・ Cache operation

Processor Request

・ Read

・ Write

Processor Request

・ Read

・ Write

・ Null

TX4955A

External agent

Addr

345

Cycle

Master Clock

SysAD Bus

WrRdy*

ValidOut*

Addr

Data

Dummy

Data

Dummy

Cycle

123

Write #1

Write #2

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