TMPR4955AF datasheet(107/168 Pages) TOSHIBA

107 / 168 page

Chapter 6 TX4955A System Interface

6-35

6.3.2

System Events

System events include:

•

Fetch miss in the instruction cache

•

Load miss in the data cache

•

Store miss in the data cache

•

an uncached load or store

•

actions resulting from the execution of cache instructions

When a system event occurs, the processor issues a request or a series of requests

through the system interface to access some external resource to service that event. The

system interface must be connected to an external agent that coordinates access to system

resources.

Processor requests include both read and write requests:

•

a read request supplies an address to an external agent

•

a write request supplies an address and a word or block of data to be written to an

external agent

Processor read requests that have been issued, but for which data has not yet been

returned, are said to be

pending. The processor will not issue another request while a read

is already pending. A processor read request is said to be

complete after the last transfer of

response data has been received from an external agent. A processor write request is said

to be complete after the last word of data has been transmitted.

External requests include both read responses and write requests:

•

a read response supplies a block or single transfer of data from an external agent

in response to a read request

•

a write request supplies an address and a word of data to be written to a processor

resource

When an external agent receives a read request, it accesses the specified resource and

returns the requested data through a read response, which may be returned any time after

the read request and at any data rate.

By default, the processor is the master of the system interface. An external agent

becomes master of the system interface either through arbitration, or by default after a

processor read request. The external agent returns mastership to the processor after the

external request completes and/or after the processor read request has been serviced.

6.3.3

System Event Sequences and the SysAD Bus Protocol

The following sections detail the sequence and timing of processor and external requests.

Note: The following sections describe the SysAD bus protocol; the TX4955A processor always

meets the conditions of this protocol. The TX4955A processor is capable of receiving

sequences of transactions on the bus at full protocol speed and of receiving data on

every cycle. At a minimum, the design of external agents must meet the requirements of

this protocol, and would ideally take full advantage of the maximum speed of the

TX4955A processor.

6.3.3.1

Fetch Miss

When the processor misses in the instruction cache on a fetch, it obtains a cache line

of instructions from an external agent. The processor issues a read request for the

cache line and waits for an external agent to provide the data in response to this read

request.

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